Volume 32 Issue 7
Jun.  2020
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Yang Jing, Cao Jianshe, Du Yaoyao, et al. Design and implementation of digital delay and pulse generator of BEPC II linear accelerator[J]. High Power Laser and Particle Beams, 2020, 32: 074001. doi: 10.11884/HPLPB202032.200018
Citation: Yang Jing, Cao Jianshe, Du Yaoyao, et al. Design and implementation of digital delay and pulse generator of BEPC II linear accelerator[J]. High Power Laser and Particle Beams, 2020, 32: 074001. doi: 10.11884/HPLPB202032.200018

Design and implementation of digital delay and pulse generator of BEPC II linear accelerator

doi: 10.11884/HPLPB202032.200018
  • Received Date: 2020-01-15
  • Rev Recd Date: 2020-04-07
  • Publish Date: 2020-06-24
  • A digital delay and pulse generator with high precision delay control, short rise time and flexible parameter adjustment is designed to meet the needs of BPM electronics for external trigger signals in the process of upgrading the BEPC II linear accelerator. An FPGA is used as the main controller. This paper mainly introduces the design principle and simulation results of edge detection module and multi-channel delay processing module based on FPGA software platform, and describes the design of FPGA and drive circuit, and its application in linear accelerator. The test results show that the output pulse of the digital delay generator has an adjustable delay range of 4 ns~4 μs, a minimum step of 4 ns, an adjustable error of 0.125%, a rise time of 2 ns, and a delay jitter of 135.4 ps.
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