Single event latch-up effect and mitigation technique in different sized CMOS devices
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摘要: 基于建立的不同工艺尺寸的CMOS器件模型，利用TCAD器件模拟的方法，针对不同工艺CMOS器件，开展了不同工艺尺寸CMOS器件单粒子闩锁效应(SEL)的研究。研究表明，器件工艺尺寸越大，SEL效应越敏感。结合单粒子闩锁效应触发机制，提出了保护带、保护环两种器件级抗SEL加固设计方法，并通过TCAD仿真和重离子试验验证防护效果，得出最优的加固防护设计。结果表明，90 nm和0.13 m CMOS器件尽量选用保护带抗SEL结构，0.18 m或更大工艺尺寸CMOS器件建议选取保护环抗SEL结构。Abstract: Based on the designed models of 90 nm, 0.13 m and 0.18 m CMOS devices, the single event latch-up (SEL) effect of different sized CMOS devices have been studied by TCAD. It shows that with the increase of process dimension of the CMOS devices, the CMOS devices will be more sensitive to SEL, while they are not SEL hardened. According to the trigger mechanism of SEL effect, two SEL preventing layouts (the structures of guard band and guard ring) were designed. Finally, the two types of structures were verified with TCAD and heavy ions facilities. The results suggest that for 90 nm and 0.13 m CMOS devices, the guard band structure is better, for 0.18 m CMOS device, the guard ring structure is recommended.
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