一种FPGA芯片在射频干扰下的失效机理

刘健; 陈弟虎; 粟涛

doi:10.11884/HPLPB201931.190161

一种FPGA芯片在射频干扰下的失效机理

doi: 10.11884/HPLPB201931.190161

中山大学电子与信息工程学院, 广州 510006

基金项目:

国家自然科学基金资助项目 61471402

广东省科技项目 2016B010123005

广东省科技项目 2015B090912001

广东省科技项目 2017B0909005

详细信息

作者简介:
刘健(1994—)，男，硕士研究生，从事可编程器件电磁兼容与电磁环境效应；liuj535@mail2.sysu.edu.cn

通讯作者:
粟涛(1977—)，男，副教授，从事集成电路射频电动力学；sutao@mail.sysu.edu.cn

中图分类号: TN432
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- 被引次数: 0
出版历程
- 收稿日期: 2019-05-13
- 修回日期: 2019-06-11
- 刊出日期: 2019-09-15

Failure mechanism of a kind of FPGA chip under RF interference

School of Electronics and Information Technology, Sun Yat-Sen University, Guangzhou 510006, China

摘要

摘要: 研究了一种Xilinx公司FPGA芯片XC7A200T-2FBG676在射频干扰下的失效机理。通过对该FPGA内核供电引脚注入射频干扰发现，某些频率下，随着干扰强度的增大，FPGA会依次出现三种不同类型的失效，分别为该FPGA的内核失效、I/O失效和配置失效。测试分析和HSPICE仿真表明，内核失效是由于BRAM的逻辑层抗扰性差所致，I/O失效是由于射频干扰下输入/输出信号的同时失真所致，配置失效则是由于配置系统读取错误的配置使能信号所致。研究可为该FPGA芯片或者系统电磁兼容设计以及该FPGA抗扰性检测方案的制定提供指导。
- FPGA /
- 射频干扰 /
- FPGA内核 /
- FPGA失效
Abstract: The failure mechanism of Xilinx's FPGA chip XC7A200T-2FBG676 under RF interference is studied. When RF interference injects into the power supply pins of the FPGA core, it is found that with the increase of interference intensity at the some frequencies, three types of FPGA failures occur successively, namely core failure, I/O failure and configuration failure. Test analysis and HSPICE simulation show that the core failure is due to the poor disturbance immunity of the logic layer of BRAM, the I/O failure is due to the simultaneous distortion of input/output signals under RF interference, and the configuration failure is due to the configuration system reading the wrong configuration enable signal. This study could provide guidance for the electromagnetic compatibility design of this kind of FPGA chip or system, as well as the formulation of electromagnetic immunity detection scheme of this kind of FPGA.
- FPGA /
- radio-frequency interference /
- FPGA core /
- FPGA failure

HTML全文

图 1 反馈信号在EMI下的变化：正常情况(a)，电平失配(b)和周期失配(c)

Figure 1. Change of feedback signal under EMI: normal state(a), level mismatch(b) and cycle mismatch(c)

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图 2 FPGA测试程序①(a)和程序②(b)

Figure 2. Testing programs for FPGA

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图 3 程序①时序图

Figure 3. Sequence diagram of program of ①

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图 4 FPGA EMI测试系统

Figure 4. FPGA EMI test system

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图 5 FPGA EMI测试板

Figure 5. FPGA EMI test board

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图 6 正常状态反馈信号特征图

Figure 6. Characteristic diagram of feedback signals in normal state

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图 7 I/O失效时反馈信号特征(a)和其滤波后特征(b)

Figure 7. Feedback signal feature (a) and its filtered feature (b) when I/O fails

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图 8 配置失效时反馈信号特征

Figure 8. Feedback signal feature when configuration fails

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图 9 内核失效时反馈信号(a)和BRAM输出特征图(b)

Figure 9. Feedback signal feature (a) and BRAM output feature (b) when core fails

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图 10 FPGA失效曲线图

Figure 10. FPGA failure curves: 520 MHz~550 MHz(a), 750 MHz~890 MHz(b) and 1030 MHz~1130 MHz(c)

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图 11 Xilinx 7系列FPGA SPI x1/x2配置时序图^[10]

Figure 11. Timing diagram of Xilinx 7 series FPGA SPI x1/x2 configuration^[10]

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图 12 输入至内核EMI仿真模型

Figure 12. Input to the core EMI simulation model

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图 13 EMI对输入到内核波形的影响

Figure 13. EMI Influence on waveform of input to thecore

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图 14 配置失效过程

Figure 14. Configuration failure process

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图 15 内核至输出EMI仿真模型

Figure 15. Core to the input EMI simulation model

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图 16 EMI下电平提升现象

Figure 16. EMI level rise phenomenon

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图 17 I/O失效过程

Figure 17. I/O failure process

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