15 nm Bulk nFinFET器件性能研究及参数优化

侯天昊; 范杰清; 赵强; 张芳; 郝建红; 董志伟

doi:10.11884/HPLPB202436.230169

15 nm Bulk nFinFET器件性能研究及参数优化

doi: 10.11884/HPLPB202436.230169

1.
华北电力大学电气与电子工程学院，北京 102206
2.
北京应用物理与计算数学研究所，北京 100094

详细信息

作者简介:
侯天昊，houtianhao97@163.com

通讯作者:
赵　强，zhaoq@iapcm.ac.cn。

中图分类号: TN386.1
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- 文章访问数: 113
- HTML全文浏览量: 43
- PDF下载量: 44
- 被引次数: 0
出版历程
- 收稿日期: 2023-06-05
- 修回日期: 2023-12-15
- 录用日期: 2023-12-15
- 网络出版日期: 2024-01-04
- 刊出日期: 2024-02-29

Performance research and parameter optimization of 15 nm Bulk nFinFET device

1.
School of Electrical and Electronic Engineering, North China Electric Power University, Beijing 102206, China
2.
Institute of Applied Physics and Computational Mathematics, CAEP, Beijing 100094, China

摘要

摘要: 为研究Bulk FinFET工作时基本结构参数、器件温度和栅极材料对其性能的影响，建立了一个15 nm n型Bulk FinFET器件模型，仿真分析了不同栅长、鳍宽、鳍高、沟道掺杂浓度、器件工作温度、栅极材料对器件性能的影响，发现增长栅长、降低鳍宽和增加鳍高有助于抑制短沟道效应；1×10¹⁷ cm⁻³以下的低沟道掺杂浓度对器件特性影响不大，但高掺杂会使器件失效；器件工作温度的升高会导致器件性能的下降；采用高K介质材料作为栅极器件性能优于传统材料SiO₂。
- Bulk FinFET /
- 短沟道效应 /
- 器件性能 /
- 参数优化 /
- 栅极材料
Abstract: Due to the growing severity of the short-channel effect in semiconductor devices, a new type of device, the FinField-Effect Transistor (FinFET), has been proposed, developed and applied. This paper aims to establish a 15 nm n-type Bulk FinFET device model to investigate the impact of basic structural parameters, device temperature, and gate material on the performance of Bulk FinFETs. Simulations are conducted to analyze the effect of different gate lengths, fin widths, fin heights, channel doping concentration, device operating temperature, and gate materials on the performance of FinFETs. The results show that increasing the gate length, decreasing the fin width, and increasing the fin height can effectively suppress the short-channel effect. Moreover, the channel doping concentration below 1×10¹⁷ cm⁻³ has little effect on the device characteristics, while high doping concentration causes device failure. Additionally, increasing the operating temperature leads to device performance degradation. Finally, using high K dielectric material as the gate material is found to enhance device performance compared to using conventional SiO₂ material.
- Bulk FinFET /
- short channel effect /
- device performance /
- parameter optimization /
- gate material

HTML全文

图 1 FinFET模型示意图

Figure 1. Schematic diagram of FinFET model

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图 2 添加量子修正项与不添加量子修正项的I_d-V_g曲线对比图

Figure 2. Comparison of I_d-V_g curves with and without quantum correction items

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图 3 不同栅长下Bulk FinFET的I_d-V_g曲线

Figure 3. I_d-V_g curves with different gate lengths

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图 4 不同栅长下的I_d-V_d曲线

Figure 4. I_d-V_d curves with different gate lengths

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图 5 不同鳍宽下的I_d-V_g曲线

Figure 5. I_d-V_g curves with different fin widths (V_d = 0.05 V)

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图 6 不同鳍宽下的I_d-V_d曲线

Figure 6. I_d-V_d curves with different fin widths (V_g = 0.8 V)

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图 7 不同鳍高下的I_d-V_g曲线

Figure 7. I_d-V_g curves with different fin heights (V_d = 0.05 V)

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图 8 不同鳍高下的I_d-V_d曲线

Figure 8. I_d-V_d curves with different fin heights (V_g = 0.8 V)

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图 9 掺杂示意图

Figure 9. Schematic diagram of doping

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图 10 不同沟道掺杂浓度下的I_d-V_g曲线

Figure 10. I_d-V_g curves with different channel doping concentrations

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图 11 不同沟道掺杂浓度下的I_d-V_d曲线

Figure 11. I_d-V_d curves with different channel doping concentrations

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图 12 不同器件温度下的I_d-V_g曲线

Figure 12. I_d-V_g curves with different device temperatures

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图 13 栅极氧化层材料示意图

Figure 13. Schematic of gate oxide layer material

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图 14 不同栅极材料下的I_d-V_g曲线

Figure 14. I_d-V_g curves with different gate materials

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表 1 不同栅长下V_T、SS、DIBL

Table 1. V_T, SS and DIBL under different gate lengths

gate length/nm	V_T/V	SS/mV	DIBL/(mV·V⁻¹)
10	0.3058	72.0845	20.53
15	0.3041	67.6268	18.55
20	0.3082	65.1960	12.57
25	0.3117	64.0744	0.92
30	0.3149	63.4691	0.80

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表 2 不同鳍宽下V_T、SS、DIBL

Table 2. V_T, SS and DIBL under different fin widths

fin width/nm	V_T/V	SS/mV	DIBL/(mV·V⁻¹)
1	0.3041	67.6269	5.42
3	0.3178	75.1745	10.84
5	0.3241	82.8697	18.53
7	0.3306	89.7392	25.62

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表 3 不同鳍高下V_T、SS、DIBL

Table 3. V_T, SS and DIBL under different fin heights

fin height/nm	V_T/V	SS/mV	DIBL/(mV·V⁻¹)
5	0.3045	70.5220	63.03
8	0.3051	69.0909	61.46
10	0.3041	67.6269	59.80
15	0.2983	65.4408	57.38
18	0.2937	67.1448	54.73

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表 4 不同沟道掺杂浓度下V_T、SS、DIBL

Table 4. V_T, SS and DIBL under different channel doping concentrations

channel doping concentration/cm⁻³	V_T/V	SS/mV	DIBL/(mV·V⁻¹)
1×10¹³	0.3042	67.5652	21.19
1×10¹⁵	0.3041	67.5704	21.33
1×10¹⁷	0.3041	67.6269	19.70
1×10¹⁹	0.3166	67.6392	44.29
1×10²¹	0.6179	76.4825	97.29

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表 5 不同器件温度下V_T、SS、DIBL

Table 5. V_T, SS and DIBL under different device temperatures

device temperature/K	V_T/V	SS/mV	DIBL/(mV·V⁻¹)
300	0.3041	67.6269	18.53
373	0.2620	86.6025	23.25
425	0.2282	101.2728	27.31

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表 6 不同栅极材料下V_T、SS、DIBL

Table 6. V_T, SS and DIBL under different gate materials

gate materials	g_max/mS	SS/mV	V_T/V	DIBL/(mV·V⁻¹)
SiO₂	8.87×10⁻⁶	65.34	0.2811	22.3
Si₃N₄	9.19×10⁻⁶	64.81	0.2722	18.4
HfO₂	9.54×10⁻⁶	64.39	0.2736	6.4

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