Design and implementation of linear injector timing system for 300 MeV proton and heavy ion accelerator
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摘要: 针对哈尔滨工业大学空间环境地面模拟装置（SESRI）-300 MeV质子重离子加速器直线注入器，设计了直线定时系统，为脉冲工作模式的直线注入器斩波器、高频低电平系统、束流诊断与反馈系统提供精准的、符合物理调束需求的工作时序触发信号。系统硬件基于现场可编程门阵列（FPGA）设计和开发，实现了内触发模式与外触发模式两种模式下对直线加速器相关设备的精准时序控制以及斩波器的控制与安全联锁。硬件支持光信号通信、W5300以太网通信、多路继电器输出与多路同步触发信号的精准时序输出。同时，系统采用光信号通信模块方便系统的级联，易于系统扩展，可满足大规模直线加速器定时系统需求。用户上位机软件基于实验物理和工业控制系统（EPICS）分布式架构开发。该系统已成功运用在300 MeV质子重离子加速器装置、近代物理研究所SSC-LINAC装置，且长期运行稳定、可靠，无任何故障。
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关键词:
- 空间环境地面模拟装置 /
- 直线定时系统 /
- 可编程门阵列 /
- 实验物理和工业控制系统 /
- 时序控制
Abstract: A linear timing system was designed for the linear injector of the Harbin Institution of Technology’s Space Environment Simulation and Research Infrastructure (SESRI) -300 MeV proton and heavy ion accelerator. The linear timing system provides precise timing trigger signals for linear accelerator chopper system with pulse operation mode, low-level RF control system, beam current diagnostic and feedback system to meet the demands of physical beam tuning. The system hardware based on the design of Field Programmable Gate Array (FPGA), which realizes the precise timing control of related equipment of linear timing system in internal trigger mode and external trigger mode, as well as the control and safety interlock of chopper. The hardware can realize the optical signal communication, W5300 Ethernet communication, multiple relay outputs and multiple synchronized trigger signals with precise timing outputs. At the same time, the use of optical signal communication module will facilitate the cascade of systems and system scalability, which can meet the large-scale needs of linear gas pedal timing system. The user high level software is developed based on the distributed architecture of EPICS (Experimental Physics and Industrial Control System). The linear timing system has been successfully used in 300 MeV proton and heavy ion accelerator and SSC-LINAC of Institute of Modern Physics (IMP), and has operated stably and reliably for a long period of time without any failure.-
Key words:
- SESRI /
- linear timing system /
- FPGA /
- EPICS /
- temporal control
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图 1 内触发模式下直线定时系统触发相关设备时序图
Figure 1. Timing diagram of linear timing system triggering related devices in internal trigger mode
图 2 外触发模式下(微脉冲、宏脉冲)工作方式直线定时系统触发相关设备时序图
Figure 2. Timing diagram of linear timing system triggering related devices in external trigger mode (micro pulse, macro pulse)
图 3 直线定时系统硬件总体框图
Figure 3. General block diagram of linear timing system and Chopper control system hardware system
图 4 内触发T0通道（基准）状态机
Figure 4. T0 channel (reference) state machine in internal trigger mode
图 5 内触发/外触发模式下同步触发输出通道状态机
Figure 5. Synchronized trigger output channel state machine in internal/external trigger mode
图 6 外触发模式下光事例输入信号解析流程图
Figure 6. Diagram of optical example input signal analysis in external trigger mode
图 7 基于FPGA的W5300通信电路框图
Figure 7. Block diagram of FPGA-based W5300 communication circuit
图 10 内触发模式下同步触发信号测试图
Figure 10. Synchronized trigger signal test chart in internal trigger mode
图 11 外触发模式下同步触发信号测试图
Figure 11. Synchronized trigger signal test chart in external trigger mode
图 12 内触发模式下A-B通道间延时准确度测试图
Figure 12. Jitter test chart between channels A-B in internal trigger mode
表 1 直线定时控制EPICS记录类型及结构体定义
Table 1. Definition of linac timing control
definition of record type for Chopper definition of struct for Chopper recordtype(Chopper) {
include "dbCommon.dbd"
field(mPulsePeriod,DBF_FLOAT) {
promptgroup (GUI_INPUTS)
asl(ASL0)
pp(TRUE)
}
field(modeChoice,DBF_UCHAR) {
promptgroup(GUI_INPUTS)
asl(ASL0)
pp(TRUE)
}……
}typedef struct ChopperRecord {
char name[61]; /* Record Name */
char desc[41]; /* Descriptor */
char asg[29]; /* Access Security Group */
epicsEnum16 scan; /* Scan Mechanism */
……
epicsFloat32 mPulsePeriod;
epicsUInt8 modeChoice;
……
Char ip[16]; /* IP address */
epicsInt32 port; /* port */
} ChopperRecord;
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表 2 内触发模式下A通道输出抖动测试结果
Table 2. A-channel output jitter statistics in internal trigger mode
description бsd max min p-p test number maximum of cycle-cycle minimum of cycle-cycle TIE1,Ch1 15.393ps 36.178ps −36.155ps 72.333ps 975 56.314ps −62.164ps current acquisition 15.015ps 29.386ps −34.661ps 64.047ps 65 49.640ps −48.016ps
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