Channel error calibration of waveform digitization system based on machine learning
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摘要: 为了提升基于模拟数字转换（ADC）技术的波形数字化读出系统的性能，提出了一种多通道间失配误差估计校准方法。采用两片国产高速ADC组成并行交替采样（TIADC）系统，采用粒子群算法（PSO）结合梯度下降法（GD）来完成系统通道失配误差估计；利用滤波器方程组和Kaiser窗截断处理得到补偿校准滤波器系数值。该补偿方法可以直接在以现场可编程门阵列（FPGA）为处理芯片的TIADC硬件平台上实现，达成宽带并行交替采样信号的在线重构。实验结果表明，该算法可以有效实现通道失配误差的补偿校准，在Vivado开发软件平台行为级仿真条件下使无杂散动态范围（SFDR）由32.1 dBFS提升到53.1 dBFS，在硬件系统测试时使SFDR提升到60.8 dBFS，且该信号重构方法易在硬件系统实现，不受通道数目的限制。Abstract: To improve the performance of waveform digital readout systems based on Analog to Digital Converter (ADC) technology, this paper proposes a multi-channel mismatch error estimation calibration method. It uses two domestically produced high-speed ADCs to form a Time-interleaved A/D Conversion (TIADC) system, and the estimation of channel mismatch error (Gain, Time-skew and Offset) can be obtained by integrating particle swarm optimization (PSO) algorithm and gradient descent (GD) method. Meanwhile, it uses filter equations and Kaiser window truncation to obtain compensation calibration filter coefficient values. This compensation method can be directly implemented on the TIADC hardware platform using Field-Programmable Gate Array(FPGA) as the central processing unit. Moreover, this algorithm can achieve online reconstruction of sampling system data. The experimental results show that the algorithm can effectively compensate for channel mismatch errors, and using the behavior level simulation of Vivado development software, the spurious free dynamic range (SFDR) is increased from 32.1 dBFS to 53.1 dBFS, the SFDR is improved to 60.8 dBFS during hardware platform testing. This signal reconstruction method is also easy to implement in hardware systems and is not limited by the number of channels.
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图 1 M通道TIADC并行交替采样系统数学模型
Figure 1. Mathematical model of M-channel TIADC sampling system
图 2 通道失配误差估计算法迭代过程
Figure 2. Iterative process of channel mismatch error estimation algorithm
图 3 双通道采样系统正弦波信号校准前后时域和频谱图
Figure 3. Time domain and spectrogram of sine wave signal before and after calibration in dual channel sampling system
图 5 时间相位误差测试结果与算法估计结果图
Figure 5. Test and algorithm estimation results of time-skew error
图 6 800 MHz信号输入校准前后信号频谱对比图
Figure 6. Comparison of 800 MHz input signal spectrum before and after calibration
表 1 重构算法FPGA硬件资源消耗
Table 1. FPGA resource consumption for reconstruction algorithm
resource type total number of resources resource consumption utilization rate/% LUT 433200 138624 32 BRAM 1470 780 53 DSP48E 3600 1520 42 FF 866400 103968 12 
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