Design and test of FPGA-TDC based on two-stage time interpolation
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摘要: 提出一种结合多相时钟与延迟链插值的多通道FPGA-TDC结构，以降低工作频率、提升线性度并减少资源消耗，同时保持高分辨率。设计采用两级插值结构，利用多相时钟与延迟链构建细时间单元，从而减小延迟非线性积累并缩小编码器规模。系统在Xilinx ZYNQ-
7035 平台实现，并在0～16000 ps范围内进行测试。实验结果表明，本文所设计的TDC系统分辨率优于4 ps，微分非线性在−1～+7 LSB之间，积分非线性在−2 LSB至+14 LSB之间。与传统结构相比，该方案在同频率下延迟链长度成倍缩短，在相同链长下频率更低。所提两级插值结构在提升分辨率和线性度的同时显著节省逻辑资源，具备良好的应用潜力。Abstract:Background Field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) have been extensively employed for high-precision time interval measurements, in which picosecond-level resolution is often required. Among existing approaches, the delay-line method remains widely used, while the system clock frequency and the delay chain design are recognized as the primary factors affecting resolution and linearity.Purpose The objective of this study is to develop a multi-channel FPGA-TDC architecture that integrates multiphase clocking with delay-line interpolation, thereby lowering the operating frequency, improving linearity, and reducing hardware resource utilization, while maintaining high measurement resolution.Methods A two-stage interpolation scheme was introduced, where fine time measurement cells were implemented through the combination of multiphase clocks and shortened delay chains. This configuration mitigates the accumulation of nonlinearity in the delay elements and reduces the scale of thermometer-to-binary encoders, resulting in decreased logic overhead. The proposed TDC was implemented on a Xilinx ZYNQ-7035 device, and its performance was evaluated within a measurement range of 0–16000 ps.Results The experimental evaluation demonstrated that a time resolution better than 4 ps was achieved. The measured differential nonlinearity (DNL) was in the range of −1 least significant bit (LSB) to +7 LSB, while the integral nonlinearity (INL) ranged from −2 LSB to +14 LSB. Compared with conventional architectures, the proposed scheme shortens the delay chain length by several times at the same operating frequency, and achieves lower frequency with the same chain length.Conclusions The proposed two-stage interpolation architecture not only enhances resolution and linearity but also significantly reduces logic resource consumption, demonstrating strong application potential. -
图 4 第二级插值阶段中并行延迟链以及计“1”编码器示意图
Figure 4. Schematic of parallel delay chains and ones counter encoder in second stage interpolation
图 7 相位段之间的间隔一致性测试结果
Figure 7. Interval consistency test results between phase segments
图 8 通道0各个相位下延迟链位宽测试结果
Figure 8. Test results of delay chain bit width under each phase of channel 0
表 1 资源占用详情
Table 1. Details of FPGA resource usage at four channels
resource utilization available utilization/(%) LUT 10007 171900 5.82 LUTRAM 241 70400 0.34 FF 20985 343800 6.10 BRAM 4 500 0.80 IO 6 250 2.40 BUFG 12 32 37.50 MMCM 2 8 25.00 
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表 2 TDC系统各通道的分辨率和精度
Table 2. Resolution and accuracy of each channel of the TDC system
Channel number LSB/ps RMS/ps 1 3.67 13 2 3.70 15 3 3.72 14
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