Abstract: Using circuit analysis and theoretical modeling, the problem of identifying worst-case irradiation and test bias for total ionizing dose (TID) effect of CMOS circuits is studied. Small scale analog and digital circuits are introduced and analyzed, thus worst-case bias conditions are identified step by step. To digital circuits, the concept of the sensitive factor is introduced to calculate the sensitive level of circuits to TID effect under different combinations of bias during irradiation and during test. The results are validated and verified by experimental tests or circuit simulation, which proves the rationality of the identification method.