Design of synchronous controller for accelerator based on FPGA

A synchronous controller based on FPGA is designed to meet the requirements in the process of controlling injector Ⅱ of accelerator driven sub-critical system (ADS). It provides 4 synchronous pulse signals for some equipments in injector Ⅱ. The controller combines coarse delay based on FPGA and fine delay based on dedicated delay chip to improve the precision of delay and increase the adjustable ranges of period, pulse width and delay. The delay per step is 0.25 ns. Delay, period and pulse width range from 1 s to 2 s. The standard deviation of period jitter is 70 ps. The output signals meet the specified requirements. The program of this controller is easy to operate, and the remote control is stable and reliable.