Development of 10 kV nanosecond pulse power supply with fast leading edge

Wang Yiming; Wang Lingyun; Zhang Dongdong; Zhou Yuan; Wang Zhiqiang; Liu Zheng; Kong Youjun

doi:10.11884/HPLPB202537.240406

Volume 37 Issue 3

Feb. 2025

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Wang Yiming, Wang Lingyun, Zhang Dongdong, et al. Development of 10 kV nanosecond pulse power supply with fast leading edge[J]. High Power Laser and Particle Beams, 2025, 37: 035001. doi: 10.11884/HPLPB202537.240406

Citation:

Wang Yiming, Wang Lingyun, Zhang Dongdong, et al. Development of 10 kV nanosecond pulse power supply with fast leading edge[J]. High Power Laser and Particle Beams, 2025, 37: 035001. doi: 10.11884/HPLPB202537.240406

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Development of 10 kV nanosecond pulse power supply with fast leading edge

doi: 10.11884/HPLPB202537.240406

1.
School of Electrical Engineering, Dalian University of Technology, Dalian 116024, China
2.
Institute of Fluid Physics, CAEP, Mianyang 621900, China
3.
Automation and Electrical Engineering, Tianjin University of Technology and Education, Tianjin 300222, China
4.
State Grid Integrated Energy Service Group Co., Ltd., Beijing 100052, China

Received Date: 2024-11-27
Accepted Date: 2025-02-11
Rev Recd Date: 2025-02-11

Available Online: 2025-03-01

Publish Date: 2025-03-15

Abstract

Abstract

With the development of fast switching characteristics of SiC MOSFET devices, they are widely used in circuit systems that require high-speed and flexible high-voltage pulse output. Studies have shown that the on-time of SiC MOSFETs is mainly affected by the gate drive technology and its implementation. Accordingly, related studies have mostly focused on the optimization of its gate drive method. In this study, a SiC MOSFET gate drive circuit was parametrically tested and optimized, and applied to ultra-fast conduction SiC MOSFET devices to achieve a significant reduction in on-time. To verify the optimization effect, the research team designed and prepared an optimized prototype of the gate boost driver for experimental testing. The test data show that the optimized gate drive voltage regulation method effectively improves the device performance, with a pulse voltage rising edge time of up to 27 ns under 10 kV voltage level and 50 A current conditions.
- solid-state switching in series,
- driving loop parameter optimization,
- fast front,
- SiC MOSFET

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References(25)

References

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