Design and test of FPGA-TDC based on two-stage time interpolation

Tong Tao; Ge Liang; Zhang Wei

doi:10.11884/HPLPB202638.250018

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Tong Tao, Ge Liang, Zhang Wei. Design and test of FPGA-TDC based on two-stage time interpolation[J]. High Power Laser and Particle Beams. doi: 10.11884/HPLPB202638.250018

Citation:

Tong Tao, Ge Liang, Zhang Wei. Design and test of FPGA-TDC based on two-stage time interpolation[J]. High Power Laser and Particle Beams. doi: 10.11884/HPLPB202638.250018

Tong Tao, Ge Liang, Zhang Wei. Design and test of FPGA-TDC based on two-stage time interpolation[J]. High Power Laser and Particle Beams. doi: 10.11884/HPLPB202638.250018

Citation:

Tong Tao, Ge Liang, Zhang Wei. Design and test of FPGA-TDC based on two-stage time interpolation[J]. High Power Laser and Particle Beams. doi: 10.11884/HPLPB202638.250018

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Design and test of FPGA-TDC based on two-stage time interpolation

doi: 10.11884/HPLPB202638.250018

Tong Tao^{1, 2
,},
Ge Liang^{1, 2
,
,},
Zhang Wei¹

1.
Institute of modern physics, Chinese Academy of Sciences, Lanzhou 730000, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China

Received Date: 2025-01-19
Accepted Date: 2025-08-02
Rev Recd Date: 2025-09-28

Available Online: 2025-11-20

Abstract

Abstract

Background
Field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) have been extensively employed for high-precision time interval measurements, in which picosecond-level resolution is often required. Among existing approaches, the delay-line method remains widely used, while the system clock frequency and the delay chain design are recognized as the primary factors affecting resolution and linearity.
Purpose
The objective of this study is to develop a multi-channel FPGA-TDC architecture that integrates multiphase clocking with delay-line interpolation, thereby lowering the operating frequency, improving linearity, and reducing hardware resource utilization, while maintaining high measurement resolution.
Methods
A two-stage interpolation scheme was introduced, where fine time measurement cells were implemented through the combination of multiphase clocks and shortened delay chains. This configuration mitigates the accumulation of nonlinearity in the delay elements and reduces the scale of thermometer-to-binary encoders, resulting in decreased logic overhead. The proposed TDC was implemented on a Xilinx ZYNQ-7035 device, and its performance was evaluated within a measurement range of 0–16000 ps.
Results
The experimental evaluation demonstrated that a time resolution better than 4 ps was achieved. The measured differential nonlinearity (DNL) was in the range of −1 least significant bit (LSB) to +7 LSB, while the integral nonlinearity (INL) ranged from −2 LSB to +14 LSB. Compared with conventional architectures, the proposed scheme shortens the delay chain length by several times at the same operating frequency, and achieves lower frequency with the same chain length.
Conclusions
The proposed two-stage interpolation architecture not only enhances resolution and linearity but also significantly reduces logic resource consumption, demonstrating strong application potential.
- time-to-digital converter,
- two-stage interpolation,
- field programmable gate array,
- multiphase clock,
- tapped delay line

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References(16)

References

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