Predistortion model of klystron based on Field Programmable Gate Array (FPGA)
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摘要: 合肥红外自由电子激光（IR-FEL）是一个工作在中红外和远红外波段的自由电子激光装置，为达到其设计指标，需要使用低电平系统（LLRF）对加速腔内加速场的幅度和相位进行监测和控制。但是速调管的输入输出非线性特性，使得近饱和区控制增益降低，导致了反馈效率的降低。设计了基于可编程逻辑阵列（FPGA）的预失真模型对速调管的幅度非线性特性进行修正，并且对2048节点直接查找表算法和32节点线性插值查找表算法进行了比较和在线实验。比较结果显示，在准确度满足要求情况下，直接查找表算法比线性插值查找表算法延迟减少25%，并且资源消耗量要少于线性插值查找表算法。采用基于直接查找表算法的预失真模块在东芝E3729型号速调管上进行了反馈效率的比较，添加预失真模块后反馈效率提高了43%。Abstract: Hefei Infrared Free Electron Laser (IR-FEL) is a free electron laser device operating in mid-infrared and far-infrared. To achieve its design targets, a low level radio frequency (LLRF) system is needed to monitor and control the amplitude and phase of the acceleration field in the accelerator cavity. However, the input-to-output nonlinear characteristic of the amplitude of the klystron decreases the control gain near the saturated region, which reduces the efficiency of feedback. In this paper, a predistortion algorithm based on FPGA is designed to correct the nonlinear characteristics of the amplitude of the klystron, and the 2048-node direct lookup-table algorithm and the 32-node lookup-table with linear interpolation algorithm are compared and tested online. The comparison shows that, in the condition of accuracy requirement, the direct lookup-table algorithm consumes 25% less clocks than the lookup-table with linear interpolation algorithm, with less total resource consumption. The feedback efficiency is compared on Toshiba E3729 klystron, and it is improved by 43% after adding the direct lookup-table algorithm based predistortion module.
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图 1 合肥红外自由电子激装置直线加速器布局图
Figure 1. Layout of the linear accelerator of Hefei Infrared Free Electron Laser (IR-FEL)
图 2 速调管输入输出幅度特性曲线
Figure 2. Input-to-output characteristic of the amplitude of the klystron
图 5 基于查找表的预失真算法流程图
Figure 5. Schematic of the lookup-table-based klystron predistortion
图 6 速调管实际输入输出曲线与基于2048节点直接查找表算法和基于32节点的线性插值的查找表算法的误差仿真
Figure 6. Simulation of error between actual input and output curves of klystron and 2048-node direct lookup-table algorithm and 32-node lookup-table with linear interpolation algorithm
图 7 216 kV下速调管预失真前后的输入输出幅度曲线
Figure 7. Input to output amplitude curve of klystron (216 kV) before and after predistortion
图 8 使用与未使用预失真算法时幅度反馈效率比较
Figure 8. Comparison of feedback efficiency with linearization and without linearization
表 1 FPGA实现结果
Table 1. Results of FPGA implementation
algorithm Lin[clk.cyc] logic elements error LUT slice sum direct lookup-table 5 881 385 1266 7.40% lookup-table with linear interpolation 7 940 500 1440 7.20% Note: Lin is namber of clocks consumed by different algorithms. 
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