Upset and damage effects and mechanisms of CMOS NAND gate caused by electromagnetic pulses

Sun Yi; Chai Changchun; Liu Yuqian; Li Fuxing; Yang Yintang

doi:10.11884/HPLPB202133.210316

Volume 33 Issue 10

Oct. 2021

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Sun Yi, Chai Changchun, Liu Yuqian, et al. Upset and damage effects and mechanisms of CMOS NAND gate caused by electromagnetic pulses[J]. High Power Laser and Particle Beams, 2021, 33: 103006. doi: 10.11884/HPLPB202133.210316

Citation:

Sun Yi, Chai Changchun, Liu Yuqian, et al. Upset and damage effects and mechanisms of CMOS NAND gate caused by electromagnetic pulses[J]. High Power Laser and Particle Beams, 2021, 33: 103006. doi: 10.11884/HPLPB202133.210316

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Upset and damage effects and mechanisms of CMOS NAND gate caused by electromagnetic pulses

doi: 10.11884/HPLPB202133.210316

1.
Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an 710071, China

Funds: supported by National Natural Science Foundation of China (61974116)

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Author Bio:
Sun Yi, 908065469@qq.com
Received Date: 2021-07-24
Rev Recd Date: 2021-10-21

Available Online: 2021-10-22

Publish Date: 2021-10-15

Abstract

Abstract

A two-dimensional electrothermal model of CMOS NAND gate is established by Sentaurus-TCAD, and the upset and damage effects and mechanisms of CMOS NAND gate are studied with the injection of electromagnetic pulse. The results show that under EMP injection, the output voltage and internal peak temperature of the device show a periodic “decline-rise”. After the EMP is removed, the output voltage stays at an abnormal value, the PMOS source current increases, the temperature keeps rising, and finally burn-out occurs in the PMOS source, due to the latch-up effect inside the device. As the pulse-width increases, the damage power threshold decreases and the damage energy threshold increases. The relationship between the pulse-width τ, the damage power threshold P and the damage energy threshold E is obtained by data fitting. The results can be used to evaluate the damage effect of EMP and provide guidance for device-level EMP anti-damage reinforcement design.
- CMOS NAND,
- electromagnetic pulse,
- upset effect,
- damage effect,
- pulse-width effect

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References(20)

References

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