Single event latch-up effect and mitigation technique in different sized CMOS devices

Based on the designed models of 90 nm, 0.13 m and 0.18 m CMOS devices, the single event latch-up (SEL) effect of different sized CMOS devices have been studied by TCAD. It shows that with the increase of process dimension of the CMOS devices, the CMOS devices will be more sensitive to SEL, while they are not SEL hardened. According to the trigger mechanism of SEL effect, two SEL preventing layouts (the structures of guard band and guard ring) were designed. Finally, the two types of structures were verified with TCAD and heavy ions facilities. The results suggest that for 90 nm and 0.13 m CMOS devices, the guard band structure is better, for 0.18 m CMOS device, the guard ring structure is recommended.