Development and application of synchronous timing system with sub-nanosecond delay resolution for accelerator devices

Zhu Peng; Zhang Yuliang; Jin Dapeng; Liu Gongfa; Huang Mingyang

doi:10.11884/HPLPB202537.240240

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Zhu Peng, Zhang Yuliang, Jin Dapeng, et al. Development and application of synchronous timing system with sub-nanosecond delay resolution for accelerator devices[J]. High Power Laser and Particle Beams. doi: 10.11884/HPLPB202537.240240

Citation:

Zhu Peng, Zhang Yuliang, Jin Dapeng, et al. Development and application of synchronous timing system with sub-nanosecond delay resolution for accelerator devices[J]. High Power Laser and Particle Beams. doi: 10.11884/HPLPB202537.240240

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Development and application of synchronous timing system with sub-nanosecond delay resolution for accelerator devices

doi: 10.11884/HPLPB202537.240240

Zhu Peng^{1, 2, 3, 4
,},
Zhang Yuliang^{2, 3, 4},
Jin Dapeng^{3, 4
,
,},
Liu Gongfa¹,
Huang Mingyang^{2, 3, 4}

1.
National Synchrotron Radiation Laboratory, University of Science and Technology of China, Hefei 230029, China
2.
Spallation Neutron Source Science Center, Dongguan 523803, China
3.
Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China
4.
University of Chinese Academy of Sciences, Beijing 100049, China

Received Date: 2024-07-22
Accepted Date: 2025-03-04
Rev Recd Date: 2025-03-04

Available Online: 2025-03-31

Abstract

Abstract

In response to the timing requirements for the commissioning and offline operation of many pre-research equipments at the China Spallation Neutron Source Phase II (CSNS-II), a synchronous timing system has been designed and developed independently based on “high-precision timing generator + low-jitter fiber optical transmission link”, which provides accurate triggers for the pre-research equipments in accordance with the physical design requirements. The hardware mainly consists of with cost-effective master boards and terminal boards, which realize strict synchronization and low-jitter transmission. Meanwhile, the master board has the ability to expand the number of output channels by using multimode optical fiber to realize the cascade connection of the hardware boards through high-speed serial transmission links; the upper software adopts adopts the method of "Serial Server + PC soft IOC" to realise the data interaction mechanism between the master board and Experimental Physics and Industrial Control System (EPICS), which can accurately configure the frequency, delay, pulse width and other parameters remotely. The synchronous timing system has been successfully used in the commissioning and operation of key pre-research equipments such as the radio frequency ion source of the CSNS-II, which has been operated stably and reliably for a long period of time. In addition, compared with commercial products, the synchronous timing system has the advantages of flexible design, strong anti-interference capability, and high versatility, which can provide a practical technical reference for the design and realisation of synchronous timing system for particle accelerator equipment at home and abroad.
- synchronous,
- FPGA,
- sub-nanosecond,
- high availability

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References(15)

References

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