Damage characteristics and physical mechanism of the CMOS inverter under  fast-rising-edge electromagnetic pulse

Ensuring the reliability of integrated circuits (ICs) has been a great challenge with the increasing complexity of the electromagnetic environment. On this basis, the fast-rising-edge electromagnetic pulse (EMP)-induced trap-assisted tunneling (TAT) effect is investigated by simulation and experiments of CMOS digital inverters. A detailed mechanism analysis is performed to explain the physical damage process. The EMP-induced field derives traps and leakage current  in the oxide, which induces output degradation and thermal failure in the device. A theoretical model of degradation and failure is established to describe the dependency of the output deterioration  and the heat accumulation  on the EMP resulting signal features. The temperature distribution function  is derived from the heat conduction equation in the semiconductor. Corresponding experiments performed based on the TLP test system substantiate the emerging performance deterioration, which is in agreement with the mechanism analysis. Simulated results from the Sentaurus TCAD indicate that EMP resulting voltage-induced damage is caused by the TAT current path occurring in the gate oxide, revealing the location susceptible to burnout. In addition, the dependency of the device failure on the pulse rising time is discussed. The mechanism analysis in this paper facilitates reinforcing the design and promotes EMP reliability research on other semiconductor devices, and the study contributes to the enhancement of EMP robustness in CMOS digital ICs.