Background Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) have become core components in high-power radio frequency (RF) communication systems. Improving the breakdown voltage of GaN HEMTs is essential for increasing operating voltage and output power, which directly enhances system communication range and detection distance. However, the influence mechanisms of gate-drain spacing (L_gd) and source field plate (FP) dimensions on breakdown characteristics under specific process conditions require systematic investigation.

Purpose This study aims to quantitatively investigate the effects of gate-drain spacing and source field plate size on the breakdown voltage of GaN HEMTs fabricated using a 0.25 μm high-voltage SiC-based GaN HEMT process, and to identify the optimal structural parameter combination for achieving enhanced breakdown performance while considering trade-offs with high-frequency characteristics.

Methods GaN HEMT devices with varying gate-drain spacings (ranging from 3 μm to 7 μm) and source field plate dimensions (from 1 μm to 4 μm) were fabricated on 6-inch SiC substrates using MOCVD-grown AlGaN/GaN epitaxial materials. The fabrication process involved photolithography, etching, metal deposition, ion implantation, and surface passivation. Breakdown voltage measurements were performed using a B1505 semiconductor analyzer and an MPI high-voltage probe station under three-terminal testing configuration with the source grounded and gate biased at −5 V to ensure complete channel pinch-off. The drain voltage was ramped from 0 V until the source-drain leakage current reached the breakdown criterion. TCAD numerical simulations incorporating Fermi-Dirac statistics, Masetti mobility models, Shockley-Read-Hall recombination, impact ionization, electron tunneling, and thermodynamic models were conducted to analyze the internal electric field distribution, potential profiles, and impact ionization rates. AC small-signal analysis was also performed to evaluate the cut-off frequency (f_T) and maximum oscillation frequency (f_Max) for different device geometries.

Results The breakdown voltage increased approximately linearly with the gate-drain spacing at a rate of about 35 V/μm. Devices with L_gd exceeding 6 μm achieved breakdown voltages greater than 300 V. The source field plate exhibited a dual-effect on breakdown voltage: as the FP size increased from 1 μm to 2 μm, the breakdown voltage increased due to improved electric field uniformity near the gate edge, reaching a maximum at L_fp = 2 μm. However, further increasing the FP size beyond 2 μm caused the breakdown voltage to decrease, attributed to the low-potential field plate compressing the effective voltage-sustaining region on the drain side. TCAD simulations confirmed that FP optimization redistributes the electric field and shifts the peak impact ionization region from the gate edge toward the drain side, enabling more uniform depletion layer extension. Regarding frequency performance, the gate-drain spacing showed a strong negative correlation with f_T and f_Max, while the field plate size exhibited only a weak positive correlation.

Conclusions Both gate-drain spacing and source field plate dimensions significantly influence the breakdown characteristics of GaN HEMTs. The breakdown voltage can be linearly enhanced by increasing the gate-drain spacing at a rate of 35 V/μm for the given 0.25 μm process, while an optimal field plate size of 2 μm maximizes the breakdown voltage. The gate-drain spacing has a dominant impact on high-frequency performance compared to the field plate. A balanced design approach is required to achieve the desired trade-off between breakdown voltage enhancement and high-frequency performance retention for specific application requirements.