Background As integrated circuit (IC) process nodes shrink and clock frequencies rise, ICs are increasingly sensitive to electromagnetic interference, and electromagnetic compatibility (EMC) has become a key factor restricting the reliability, safety, and stability of electronic systems. Electrical transients, mainly from power switching, lightning induction, and electrostatic discharge, exhibit high amplitude, short rise time, and wide spectrum, and are a primary cause of logic upset, data corruption, and even permanent failure. Although system-level EMC standards are relatively mature, PCB layout, external filtering, and shielding make it difficult to quantify the intrinsic immunity of the IC itself, masking the sensitivity vulnerabilities of key devices.

Purpose This paper focuses on two core pulse immunity test methods for IC EMC evaluation: electrical fast transient (EFT) and electrostatic discharge (ESD) testing. With the formal release of the asynchronous transient injection standard (GB/T 43034.3-2023), it concentrates on the technical principles and operational protocols of this method to promote its standardized application in IC testing. As the dedicated national standard for IC-level ESD is still under development, ESD is only briefly outlined.

Methods Following GB/T 43034.3, transient pulses with specified amplitude, rise time, and energy are injected into IC pins through conductive coupling. The coupling-network design principle, the differentiated injection strategies for power and I/O pins, and the electromagnetic-integrity requirements of the EMC test board are analyzed. Because pin-level injection removes the attenuation introduced by PCB routing and system-level peripherals, it enables accurate extraction of the device's intrinsic immunity boundary. Key technical elements, including pulse waveform parameters, severity-level settings, test configuration, calibration, and failure criteria, are elaborated, and the differentiated specifications for consumer/industrial and vehicle environments are compared through two cases: a consumer MCU and an automotive LIN transceiver.

Results For the MCU, the VDD_HV_PMC, VDD_HV_IO_FLEX, and VDD_HV_IO_MAIN rails maintained class A over the full severity range, whereas the digital core supply (VDD_LV) and the oscillator supply (VDD_HV_OSC) degraded markedly to class C/D, indicating insufficient on-chip decoupling capacitance and protection margin. For the LIN transceiver, even with a filter capacitor, the bus triggered RX1 failure under pulses 1, 2a, and 3b well below half of the maximum severity level, while only pulse 3a remained stable across all levels, revealing an asymmetry between the positive- and negative-polarity protection paths.

Conclusions The results demonstrate that standardized pulse immunity testing based on GB/T 43034.3 can effectively locate intrinsic design weaknesses, such as sensitive power domains and asymmetric polarity protection, that are difficult to identify through system-level testing. Together with synchronous EFT and ESD methods, the asynchronous transient injection method forms a comprehensive evaluation framework, providing a scientific basis for chip protection-circuit optimization, system protection configuration, and product reliability certification, and offering systematic technical support for IC EMC performance and forward design.