HIAF-BRing电源样机模块故障联锁保护系统设计与实现

谭玉莲; 吴凤军; 王晓俊; 燕宏斌; 黄玉珍; 李雨航; 李继强; 张帅; 张华剑; 朱芳芳; 高大庆

doi:10.11884/HPLPB202133.210034

HIAF-BRing电源样机模块故障联锁保护系统设计与实现

doi: 10.11884/HPLPB202133.210034

谭玉莲^{1, 2, 3,},
吴凤军^{1, 3},
王晓俊^{1, 3},
燕宏斌¹,
黄玉珍¹,
李雨航^{1, 2},
李继强¹,
张帅²,
张华剑¹,
朱芳芳¹,
高大庆^{1, 2, 3, ,}

1.
中国科学院近代物理研究所，兰州 730000
2.
中国科学院大学核科学与技术学院，北京 100049
3.
惠州离子科学研究中心，广东惠州 516003

基金项目: 国家重点研发计划项目（2019YFA0405402）；广东省创新创业团队项目（2016ZT06G373）

详细信息

作者简介:
谭玉莲（1993—），女，博士研究生，从事重离子加速器电源研究

通讯作者:
高大庆（1969—），男，博士，研究员，从事重离子加速器电源研究

中图分类号: TL503.5
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- 文章访问数: 1035
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- 被引次数: 0
出版历程
- 收稿日期: 2021-01-29
- 修回日期: 2021-04-14
- 网络出版日期: 2021-05-19
- 刊出日期: 2021-07-15

Design and implementation of module fault interlock and protection system of HIAF-BRing power supply prototype

Tan Yulian^{1, 2, 3
,},
Wu Fengjun^{1, 3},
Wang Xiaojun^{1, 3},
Yan Hongbin¹,
Huang Yuzhen¹,
Li Yuhang^{1, 2},
Li Jiqiang¹,
Zhang Shuai²,
Zhang Huajian¹,
Zhu Fangfang¹,
Gao Daqing^{1, 2, 3
, ,}

1.
Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China
2.
School of Nuclear Science and Technology, University of Chinese Academy of Sciences, Beijing 100049, China
3.
Huizhou Research Center of Ion Sciences, Huizhou 516003, China

摘要

摘要: 强流重离子加速器装置（HIAF）的增强器（BRing）二极铁电源样机采用多模块串并联的全储能快循环脉冲电源实现方案，电源功率达到MW级。由于电源规模庞大和功率巨大，为了在运行中迅速保护电源设备，设计并实现了一套双冗余的基于可编程逻辑控制器（PLC）、模块故障联锁板和现场可编程门阵列（FPGA）的模块故障联锁保护系统，利用硬件和软件同时对电源功率单元模块实施故障检测、故障传递和故障保护。设计完成后分别从电源联锁环路的响应时间、核心控制板故障引发电源环路联锁的总时间和设备故障响应等三个方面进行测试，测试结果表明，在电源发生故障时，模块故障联锁保护系统满足电源样机对实时性和可靠性的要求，达到设计目标。
- 模块故障联锁 /
- 数字控制器 /
- 故障检测 /
- 故障保护 /
- HIAF-BRing
Abstract: Power supply prototype in High Intensity heavy ion Accelerator Facility-Booster Ring (HIAF-BRing) adopts the scheme of full energy and fast cycle storage pulse power supply topology. Its multi modules are connected in series and parallel pattern, and the power reaches megawatt level. Due to the high power and large scale of the power supply, a module fault interlock protection system based on Programmable Logic Controller (PLC), interlock boards and Field Programmable Gate Array (FPGA) is designed and implemented to protect the power supply in operation. In this paper, first, a design of double redundant module fault interlock is introduced. Second, the logic implemented in PLC is described. Third, the work about FPGA is given. Finally, the system is tested in three aspects: the responsive time of the power supply interlock loop, the total time from controller error occurrence to interlock finish, and the equipment fault response. The result shows that the module fault interlock system can action sensitively, timely and reliably in case of fault occurrence, which meets the requirements of the power supply prototype in HIAF-BRing.
- module fault interlock /
- digital controller /
- fault detection /
- fault protection /
- HIAF-BRing

HTML全文

图 1 HIAF-BRing电源样机拓扑结构图

Figure 1. Topology of HIAF-BRing power supply prototype

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图 2 双冗余模块故障联锁设计

Figure 2. Design of double redundant module fault interlock

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图 3 模块故障联锁板原理图

Figure 3. Schematic of module fault interlock board

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图 4 数字控制器一个支路控制结构图

Figure 4. One branch of digital controller

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图 5 PLC故障保护机制

Figure 5. Protection mechanism in PLC

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图 6 PLC复位联锁重建时序图

Figure 6. Sequence diagram of interlock reestablish after resetting in PLC

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图 7 核心控制板故障处理时序图

Figure 7. Sequence diagram of fault handling in main control board

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图 8 数字控制器故障保护机制

Figure 8. Protection mechanism in digital controller

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图 9 核心控制器复位重建时序图

Figure 9. Sequence diagram of interlock reestablish after resetting in main control board

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图 10 现场测试及实物图

Figure 10. Photoes of test equipment and interlock board

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图 11 电源联锁环路响应时间

Figure 11. Response time of power supply interlock loop

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图 12 故障联锁单板的响应时间

Figure 12. Response time of single interlock board

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图 13 数字控制器故障时后引发电源环路联锁总时间

Figure 13. Total time from digital controller error occurrence to interlock finish

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表 1 各大工程设备联锁保护系统的实现方案

Table 1. Implementation of interlock protection system for major facility

facility	kernel	response time/μs
protection of the resonant power supply in CSNS/RCS interlock system for SXFEL high voltage power supply protection in EAST-NBI	PLC PLC & EPICS DSP, compare circuits & LabVIEW	16 000 15 000 2 600
fast interlock system in SSRF	FPGA & ARM	34

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表 2 PLC检测的故障

Table 2. Fault detected by PLC

fault	quantity of one unit	total amount of power supply prototype
cooling water fault	1	16
safeguard fault	1	16
main circuit fault	1	15
soft start fault	1	15
fuse fault	1	15
over temperature fault of transformer	1	15
emergency stop	1	16
external fault	4	64
over temperature fault of H bridge radiator	1	15
over temperature of output inductor	1	15
IGBT fault of H bridge	2	30
over temperature fault of capacitor bank	1	12
module interlock fault	1 or 2	17

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表 3 核心控制板检测的故障

Table 3. Fault detected by main control board

fault	quantity
SFP fault	3
RS485 fault	1
ADC synchronous light fault	3
IGBT fault (light)	75
power on fault	16
over output current fault	1
over branch current fault	3
over bus voltage fault	15
module interlock fault (light)	1

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表 4 高速采集板检测的故障

Table 4. Fault detected by acquisition board

fault	quantity of one board	total amount
SFP fault	2	27
RS485 fault	1	15
ADC synchronous light fault	1	15

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参考文献(15)

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