Research on full-bridge bipolar pulsed current source based on parallel SiC MOSFETs
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摘要: 为满足高功率脉冲应用对大电流双极性输出及灵活调控的需求，本文提出并实现了一种基于SiC MOSFET并联全桥拓扑的紧凑集成式双极性脉冲电源系统。该系统在单板上集成主功率级、隔离驱动、辅助电源与控制保护模块，兼具高功率密度与良好扩展性。实验结果表明：在50～300 V母线电压下，输出峰值电流与母线电压保持高度线性相关，脉宽调节实现了峰值电流的连续可控，最大增幅达37%。系统可稳定输出高达±300 A的双极性脉冲电流，充分验证了大电流输出与紧凑设计的兼容性。此外，在500$ \;ns $脉宽下四管并联的均流不均匀系数为12.87%，验证了协同驱动与独立栅极电阻设计的有效性。研究结果表明，该紧凑集成方案在大电流双极性脉冲输出与参数可调性之间实现了兼顾，为中压条件下高功率脉冲源的小型化与工程化提供了实验依据和设计参考。
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关键词:
- 双极性脉冲电流源 /
- SiC MOSFET并联 /
- 全桥拓扑 /
- 协同驱动 /
- 大电流脉冲输出
Abstract:Background High-power pulsed applications increasingly require power supplies capable of large-current bipolar output and flexible controllability. However, achieving high power density while maintaining pulse precision and current-sharing stability remains a significant challenge in pulse source design.Purpose This work aims to design and implement a compact, integrated bipolar pulsed current supply system that utilizes a paralleled Silicon Carbide (SiC) MOSFET full-bridge architecture to meet the demands of medium-voltage, high-power pulsed applications.Methods The proposed system integrates the main power stage, isolated drivers, auxiliary power supplies, and protection module on a single printed circuit board (PCB), featuring both high power density and scalability.Results Experimental results demonstrate that, under DC bus voltages from 50 V to 300 V, the peak output current exhibits excellent linear correlation with the bus voltage, while pulse-width adjustment enables continuously controllable peak current with a maximum enhancement of 37%. The system is capable of delivering bipolar pulse currents up to ±300 A, confirming the compatibility of high-current output with compact integration. In addition, at a 500$ \;ns $ pulse width, the four-device paralleled branch achieves a current-sharing imbalance factor of 12.87%, validating the effectiveness of the cooperative gate-drive scheme and the use of independent gate resistors.Conclusions These findings indicate that the proposed compact integrated design successfully balances large-current bipolar pulsed output and parameter adjustability, providing experimental evidence and design guidance for the miniaturization and engineering implementation of medium-voltage and high-power pulse sources. -
图 4 含寄生参数负载条件下的仿真波形对比
Figure 4. Simulation waveforms comparison under parasitic load conditions
图 5 不同源极寄生电感条件下的漏极电流
Figure 5. Drain current under different source parasitic inductance conditions
图 6 基于SiC MOSFET并联全桥结构的双极型电流源实验平台
Figure 6. Experimental platform for bipolar current source based on paralleled SiC MOSFET full-bridge structure
图 7 500$ \;ns $脉宽下四管并联SiC MOSFET电流均流波形
Figure 7. Four-paralleled SiC MOSFET current sharing waveforms under 500$ \;ns $ pulse width
图 8 系统在0～300 V母线电压范围内的输出电流波形
Figure 8. Output current waveforms of the system in 0-330 V DC bus voltage range
图 9 不同驱动脉宽下的输出电流特性
Figure 9. Output current characteristics under different drive pulse widths
表 1 主要电路参数
Table 1. circuit parameters
Signal
width/$ \mu s $DC bus
voltage/VEnergy storage
capacitor/$\mu F $Gate drive
resistor/$ \Omega $Ideal load
resistor/$ \Omega $Load resistor
(RL series)/$ \Omega $Load Inductance
(RL series)/$ nH $100 300 100 10 1 1 200 
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表 2 并联系统均流评价指标
Table 2. Evaluation metrics for current sharing in parallel system
Parameters MOSFET1 MOSFET2 MOSFET3 MOSFET4 $ {I}_{peak} $ 39.17 43.00 44.67 44.12 Absolute Deviation 3.57 0.26 1.92 1.38 $ CSIF $ 12.87% $ \sigma $ 13.69% 2.12% 5.26% 10.27%
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表 3 拟合参数及拟合优度指标
Table 3. Fitting parameters and fit quality indicators
Parameters k b $ {R}^{2} $ ϒ $ RSS $ Value 0.99265 4.40854 0.98911 0.99454 474.43729
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