考虑能量沉积涨落的锁相环电路总剂量辐射效应研究

Study of clock generator PLL circuit under total ionizing dose effects in consideration of energy deposition fluctuation

  • 摘要: 考虑晶体管能量沉积涨落,采用蒙卡抽样方法随机修改晶体管SPICE网表敏感参数,等效开展典型0.18 μm工艺锁相环电路(PLL)总剂量辐射效应研究,给出0~200 krad (SiO2)不同总剂量环境参数下锁相环电路的输出频率f、相位差δ和压控电压Vco_in的变化,并初步对PLL总剂量辐射效应敏感模块进行了甄别。研究结果表明,在不考虑晶体管能量沉积涨落情形下,总剂量辐射效应会导致PLL电路的δf发生不同程度的波动,但最终可通过环路反馈机制恢复正常,保持PLL电路锁相功能;相反,在考虑晶体管能量沉积涨落情形,PLL电路锁相后呈现出非预期频率的响应输出,可能导致通信过程的数据丢失以及处理器功能的扰动,对电路整体行为产生灾难性影响。如随着总剂量的增加,PLL电路输出频率分布离散性增大,在30和200 krad (SiO2)时,f的标准方差分别为83 kHz和217 kHz,相差近3倍。进一步,通过监测PLL电路各个模块的总剂量辐射效应响应,初步发现电荷泵模块对总剂量辐射效应较为敏感。本文相关研究方法、结果可为考量或评估真实条件下的PLL电路总剂量辐射效应研究提供参考,并进一步对PLL电路的抗总剂量辐射效应设计提供建议。

     

    Abstract:
    Background
    Phase-locked loops (PLL) circuit plays a significant role in microprocessor clock circuits and high-speed interface circuits. Conducting research on the strong radiation effect of PLL circuits could provide basic data for evaluating their overall damage response.
    Purpose
    In consideration of transistors’ energy deposition fluctuation to be more close to practical radiation, the total ionizing dose (TID) effect of a typical 0.18 μm process phase-locked loops circuit (PLL) was equivalently studied, which could make up for the deficiencies of previous related research.
    Methods
    Employing Monte Carlo sampling method to modify the sensitive parameters of the transistor SPICE model, the TID effect of PLL circuit was studied, where the statistical distributions of output frequency f, phase difference δ, and control voltage Vvco_in under different TID ranging from 0 to 200 krad (SiO2) are given.
    Results
    Results demonstrate that the values of f and δ would be changed in various degrees under TID effect without considering the energy deposition fluctuations, and they could eventually return to normal through the circuit’s feedback mechanism. On the contrary, when considering the energy deposition fluctuations, the PLL circuit shows an unexpected frequency response after phase locking, which may lead to data loss during the communication process and disturbances to the processor’s functionality, thus leading to a disaster’s impact on the overall behavior of the circuit.
    Conclusions
    The simulation methods and results in this paper could provide references for considering or evaluating TID effect of PLL circuits under real conditions, and further offer suggestions on the design of anti-TID effect of PLL circuits.

     

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